1. Field of the Invention
The present invention relates to a digital PLL frequency synthesizer, more particularly to, a digital PLL frequency synthesizer characterized by fast locking and low jitters.
2. Description of the Prior Arts
With rapid advance of deep sub-micron CMOS technology, the conventional PLL suffers from dropping supply voltage, smaller operating range, design complexity, and difficulty regarding to its die size shrink. For the conventional PLL, there exists a trade-off between the lock-in time and the output jitter; namely, it is very difficult to achieve fast locking and low jitters at the same time. Hence, the digital PLL design plays a major role in the recent PLL implementation.
The conventional digital PLL frequency synthesizer is depicted in FIG. 1.
As suggested in R.O.C. Patent I279085, the loop filter and the voltage-controlled oscillator in the conventional charge pump PLL are replaced by digital circuits, wherein the output phase information of a phase frequency detector 120 is sampled and quantized; due to the limited range of the oscillating frequency of a oscillator 150, therefore, there exist a lot of quantization errors and a dead zone is invited so as  unable to locking quickly and at the same time said 150 will be affected by the jitter characteristics at output side. Accordingly, in view of the above drawbacks as the foregoing, it is an imperative that a digital PLL frequency synthesizer, particularly, a digital PLL frequency synthesizer characterized in fast locking and low jitters is designed so as to improve the poor state of quantization error as disclosed in the conventional art.